Equal-amplitude signaling directional coupling bus

ABSTRACT

In ultrahigh speed data transfer, a drive pulse is attenuated due to a skin effect and a dielectric loss, and a tail generated by a sub coupler extends as the drive pulse propagates on the main line. For that reason, an intersymbol interference becomes large, which causes jitters. In a memory system to which a plurality of DRAM memory modules are connected, in order to transfer data at high-speed, directional couplers are wired between a main controller and each of the modules, and the coupling lengths become longer with farther ends, thereby suppressing jitters. The directional couplers are wired between the main controller and each of the modules, and the coupling lengths are made longer with the farther ends with the results that the generated signal amounts are made constant, and jitters of the wiring and receiver delay are suppressed.

TECHNICAL FIELD

The present invention relates to a technique for signal transmissionbetween devices such as a multiprocessor or a memory (for example,between digital circuits that are made up of MOS or between functionalblocks thereof) in an information processor, and more particularlyrelates to a high-speed technique of bus transmission that conducts datatransfer in which a plurality of devices are connected to the sametransmission line.

BACKGROUND ART

In order to transfer data at a high speed in a state where a largenumber of nodes are connected to one another, a propagation delay timeof wiring cannot be ignored. In particular, in a DDR-SDRAM (double datarate synchronous DRAM), an operating frequency of data is twice as largeas that of an address, and the effect of noises reflected from abranched wiring on a bus wiring makes high speed difficult. Examples ofmethods for solving the above problem include “non-contact bus” in JP07-141079A (U.S. Pat. No. 5,638,402), “directional coupling memorymodule” in JP 2001-027918A (U.S. Ser. No. 09/570349), and “directionalcoupling bus system” in JP 2001-027987A (U.S. Ser. No. 09/569876).

FIG. 2 shows the structure of the directional coupling bus disclosed inJP 07-141079A.

In the above method, data transfer between two nodes is conducted byusing a backward crosstalk, that is, the transformation of from an NRZsignal to an RZ signal through a directional coupler. That is, this is atechnique in which transfer between a bus master 10-1 and slaves 10-2 to10-4 is performed by using two lines, that is, the backward crosstalkbetween a wiring 20 and wirings 20-1 to 20-4. This technique is suitablefor transfer between a bus master 1 and the slaves 10-1 to 10-4, thatis, suitable for data transfer between a memory and a memory controller.In this example, directional couplers that are connected to the bus areidentical in the configuration with each other, and the couplingcoefficients (KB) and the coupling lengths L1 to L4 of those directionalcouplers are also constant.

Subsequently, in a conventional example, “directional coupling bussystem” of JP 2001-027918A, a main line 20 is folded back to provide thedirectional coupler with a multilayer structure, thereby realizing ahigh density. Similarly, the coupling lengths of the directionalcouplers are constant in this example.

In the “directional coupling memory module” of JP 2001-027987A, a wiring(main line) from a memory controller is drawn in memory modules, and adirectional coupler is structured within each of the memory modules.Similarly, in this example, the memory modules that are connected to thememory bus are identical in the configuration with each other, and thecoupling coefficients (KB) and the coupling lengths of the directionalcouplers within the memory modules are also constant.

The above conventional examples have the feature that the lengths of thedirectional couplers are constant. The reasons are as below.

In general, when a rise time of a drive pulse is shorter than apropagation delay time of reciprocating of the directional coupler, thedirectional coupler generates an amount of backward crosstalk signal notdepending on the coupling length. For that reason, a ratio of an inputvoltage to a backward crosstalk voltage gets constant not depending onthe length. In FIG. 2, if attenuation when a drive waveform from an MC 1propagates on the wiring 20 can be ignored, the production of thebackward crosstalk signals by the wirings 20-1 to 20-4 becomes constant.

For that reason, in the conventional art, when it is assumed that thedirectional coupler lengths that generate the respective crosstalks areL1 to L4, L1=L2=L3 L4 is constant, and the wiring intervals of thedirectional couplers are also identical with each other in order torealize the same coupling coefficients of the directional couplers. Thedirectional couplers that have the constant wiring intervals and lengthsgenerate substantially the same signal amount with respect to any busslaves.

As described above, in the conventional art using the directionalcouplers, the coupling lengths of the directional couplers within thebus to be used are constant, and an interval between two lines whichdetermine the coupling coefficients (Kb) is also constant.

DISCLOSURE OF THE INVENTION

Even the above arts do not suffer from any problems in a practical usewhen the data transfer rate of the main line is a high-speed transferrate of about several hundreds Mbps. This is because the directionalcouplers generate the sufficiently large signal generation with respectto the operating frequency.

However, the present inventors have advanced a research for furtherincreasing the high speed of the bus performance when being applied to amemory system. The present inventors have studied a memory system of theXTL coupling system having an ultrahigh speed transfer rate in which thedata transfer rate of the main line is about several Gbps or higher. Asa result, the present inventors have found out novel problems related toan accent of a waveform of the RZ conversion signal which isattributable to the signal conversion of NRZ to RZ, a difference in theamplitude value of the RZ conversion signal between a master close sidememory and a master far side memory, and an increase in the amount ofjitters which is attributable to the high speed.

A method of determining the coupling length of the conventionaldirectional coupler will be described below.

In FIG. 2, for example, a directional coupler that is made up of themain line 20 and the wiring 20-1 is considered. The wiring 20 is called“main coupling line”, and the wiring 20-1 is called “sub coupling line”.In the case where the drive pulse progresses on the main coupling line20 from the left toward the right on the drawing, a backward crosstalkis generated on the left end (near end) of the sub coupling line 20-1.In the case of a stripe line that is structured such that thedirectional coupler is surrounded by a power plane, a forward crosstalkthat is generated on the right end (far end) is small to the degree thatcan ignore the forward crosstalk. Even in the case of a micro strip linewhose one side is structured by an air layer, the forward crosstalk isabsorbed with a far end resistor.

When it is assumed that a rise time of the drive pulse is Tr, apropagation delay velocity of the sub coupling wire 20-1 is Vp, apropagation delay time is Td, and a wiring length is L, the directionalcoupler generates a signal of 2Td as the near end crosstalk signal underthe condition of Expression (1), and a signal amplitude at this time isthe maximum.Tr≦2*Td   (1)Td=L/Vp   (2)

For that reason, the coupling length of the directional coupler thatgenerates the maximum backward crosstalk has a relationship shown inExpression (3), and the coupling length gets the shortest when equalityis satisfied. When Expression (3) is satisfied with respect to themaximum rise time Tr when the drive pulse propagates in the maincoupling line, the respective sub coupling lines 20-1 to 20-4 shown inFIG. 2 generate signals equal in quantity at their near ends.L≧½*Tr*Vp   (3)

As described in the third problem with JP 2001-027918A, there is aphenomenon in which the high frequency components contained in the drivepulse gets large in the attenuation because of the skin effect anddielectric loss of the wiring, and therefore the rise time becomeslonger with the directional coupler farther from the MC1. For thatreason, the coupling length (L) is adjusted to Tr that becomes longer orthe forward crosstalk is used in the conventional example.

In many instances, in order to manufacture the directional coupling witha high precision, a strip line structure that forms the inner layer of amultilayer substrate is used for the directional coupler, and theforward crosstalk cannot be used. For that reason, in FIG. 2, L1 to L4are determined such that L4 satisfies Expression (3), and L1 to L3 arelonger than a desired value.

In addition, it is proved that since a transmission signal becomes highin speed, a dull waveform occurs due to the directional coupler, and anintersymbol interference becomes larger. As one example, FIG. 3A shows adrive pulse and a crosstalk signal at the time of data transfer at 500Mbps, and FIG. 3B shows a drive pulse and a crosstalk signal at the timeof data transfer in the operation of 1 Gbps. In the case where the drivepulse is transmitted, a positive pulse and a negative pulse aregenerated at times corresponding to rise and fall. In the crosstalkwaveform, both of the positive pulse and the negative pulse are shapedin a chopping wave, and the rise of the chopping wave is slower than thefall thereof.

As a result of observing the crosstalk signal waveform in more detailthrough an oscilloscope, it is found that a tail portion extends fromthe fall portion of the waveform. The portion is called “tail section”.It is presumed that the tail section is caused by a dull waveform thatoccurs when each of the drive pulse and the crosstalk signal propagatesin the directional coupler. This is because the high frequency componentcontained in the signal largely attenuates due to the skin effect andthe dielectric loss of the wiring. For that reason, the attenuationbecomes more remarkable as the distance is longer.

In FIG. 3A, since the tailsection of the positive pulse falls within acycle (T) 2 ns, the tail section does not affect the negative pulse.However, as shown in FIG. 3B, when the cycle is 1 ns, the tail sectionof the positive pulse interferes with a subsequent negative pulse withrespect to the directional couplers having the same wiring length. Thisis a phenomenon that is called “intersymbol interference” (ISI) becauseof the interference between two signals (symbols). For that reason,comparing a case having no data before one cycle of the negative pulsewith another case having data, in the case having data, a signal is sogenerated as to be superimposed on previous data, the waveforms aremisaligned. This misalignment causes jitters. This is because when thecrosstalk waveform arrives at the respective bus slaves 10-1 to 10-4 inFIG. 2, a threshold voltage that is regulated by a receiver becomesfaster or slower according to previous data.

The jitters obstruct the high-speed transfer. Also, in FIG. 2, the riseis dulled due to the skin effect as the drive pulse (NRZ signal) fromthe bus master 1 goes far away from the bus master 1. For that reason,the tail section becomes longer as the signal generated by the subcoupling lines 20-1 to 20-4 of the directional coupler is farther, andthe crosstalk signal amount becomes smaller when the coupling lengthdoes not satisfy Expression (3).

For example, a signal that propagates to the bus slave 10-4 is smallerin the signal amount than a signal that propagates to the bus slave10-1, and is duller in the waveform than the latter.

In addition, jitters occurring within the receiver become larger. Thisis because different waveforms are inputted to the receivers within thebus slaves 10-1 to 10-4. In general, in the case where the receiver hasan insufficient gain, the receiver has differences in the sensitivity ofnoises and in a delay time at which the signal passes through thereceiver due to the amplitude of the input signal. For that reason,because the receivers within the bus slaves 10-1 to 10-4 are differentfrom one another in the input signal waveform, there are differences inthe noise sensitivity and in the delay time. For that reason, whenhigh-speed data is transferred, the differences in the noise sensitivityand delay time affect the operation of the receiver, which causesjitters.

An object of the present invention is to ensure a margin of a timing soas to surely conduct signal write and signal read even when the datatransfer rate of the main line becomes ultrahigh speed. That is, thesignal amount is kept constant, and jitters are reduced. As a result,there is provided a memory system that enables high-speed operation.

In the present invention, a first problem is that since the intersymbolinterference become larger with higher speed, and a transition durationof the drive pulse is different according to the position of thedirectional coupler, the amount of jitters is also different accordingto the position of the directional coupler. For that reason, a firstobject of the present invention is to hold the timing margin of theentire system constant by making jitters occurring due to thedirectional coupler constant regardless of the position of thedirectional coupler.

In the data transfer between the bus master 1 and the bus slaves 10-1 to10-4, an amplitude difference of the signal waveform which is caused bythe arrangement is eliminated. As a result, the receiver jitters arelargely suppressed, and the noise sensitivity is held constant, therebymaking it possible to realize higher speed.

In the present invention, a second problem resides in that in the casewhere the coupling length of the directional coupler is insufficientlytaken due to the structure of the system as in the memory module, or thebus slaves must be arranged at regular intervals, the directionalcouplers are so arranged as to make the coupling length of thedirectional coupler longest, and therefore the coupling lengths mustalso be held constant. For that reason, the signal amounts occurringbetween the slaves are different from each other, which causes jitters,as in the first problem. A second object of the present invention is tohold constant, a crosstalk signal amount that is generated in each ofthe bus slaves in a state where the bus slaves are arranged at regularintervals, and the bus slave intervals are not taken as in the memorymodules.

In the present invention, the third problem resides in that since thetail section is contained in the generated waveform by the directionalcoupler, the tail section per se causes the jitters with higher speed. Athird object of the present invention is to eliminate the tail sectionand hold the signal amplitude constant to reduce the jitters.

A means for solving the first problem is that the coupling length ischanged according to the dulling of a signal that flows in thedirectional coupler to make the generated signal constant. The couplinglength is decreased in the waveform that is smaller in the dulling, andthe coupling length is increased in the waveform that is larger in thedulling.

A means for solving the second problem is the following. Even in thecase where the coupling length of the directional coupler is notsufficiently taken due to the structure of the system, or the bus slavesmust be arranged at regular intervals as in the memory module, in orderto make constant the amount of the crosstalk signal that is generated ineach of the bus slaves, the coupling coefficient of the directionalcoupler is adjusted. To achieve this structure, the wiring intervals ofthe directional couplers are made narrower as the directional couplersare farther away from the MC.

A means for solving the third problem is that a waveform that cancelsthe tail section is incorporated into the drive pulse. For example, inthe case of a rise signal, a fall signal is superimposed on the risesignal shortly after the rise time so as to cancel the tail section. Thefall signal is adjusted for each of the slaves according to the positionof the directional coupler that is connected to the bus slave, the risetime, and the waveform of the tail section. The signal amplitude can beheld constant with the elimination of the tail section, thereby makingit possible to reduce the jitters.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram for explaining a first embodiment;

FIG. 2 is a diagram showing a conventional art;

FIG. 3A is graphs showing a conventional waveform (500 Mbps) and FIG. 3Ba conventional waveform (1 Gbps);

FIG. 4 is a graph showing a directional coupler length of a module and asignal amplitude that is generated by the directional coupler;

FIG. 5A includes diagrams showing the definition of waveforms(DrivePulse) and FIG. 5B the definition of waveforms(Coupler Signal);

FIG. 6 is a diagram showing a directional coupler bus in which wiringintervals are adjusted according to a second embodiment;

FIG. 7 is a diagram (bird's eye view) showing the directional coupleraccording to the second embodiment;

FIG. 8 is a diagram showing a directional coupler bus according to athird embodiment;

FIG. 9 is a diagram showing a directional coupler bus according to afourth embodiment;

FIG. 10 is a diagram showing a directional coupler bus (memory system)according to a fifth embodiment;

FIG. 11 is a diagram showing a sixth embodiment (a main line using afolded wiring);

FIG. 12 is a diagram showing a memory bus in which a main line is foldedwithin a module according to a seventh embodiment;

FIG. 13 is a diagram showing a directional coupler bus in which thecoupling length and the coupling length of a directional coupler areadjusted;

FIG. 14 is a diagram showing a driver circuit 4 for canceling the tailsection;

FIG. 15A are graphs showing a drive waveform for canceling the tailsection and FIG. 15B a crosstalk waveform in which an intersymbolinterference is reduced; and

FIG. 16 is a diagram (bird's eye view) showing a directional couplerbus.

BEST MODE FOR CARRYING OUT THE INVENTION

A first embodiment will be described with reference to FIG. 1. This isan embodiment structuring a memory system.

Reference numeral 1 denotes an LSI chip having a memory controllercontrol mechanism (hereinafter referred to as “MC”: memory controller).References 10-1 to 10-4 denote memory chips (DRAM). In FIG. 1, fourmemories transfer data with respect to the MC 1. However, the object andthe advantages are the same regardless of the number of memories.

Reference numeral 20 is a wiring (main line) which is drawn out of theMC 1, and has a far end which is matched and terminated with atermination resistor 30 (Rtt). The wirings 20-1 to 20-4 are arranged inparallel with the main line 20 at close positions, and constitute thedirectional couplers in association with the respective parts of themain line 20. Since the wirings 20-1 to 20-4 are other wirings thatconstitute the directional couplers, those wirings are called “subcoupling lines”. The far ends of the sub coupling lines 20-1 to 20-4when being viewed from the MC1 are matched and terminated, and the nearends thereof are wired to DRAMs 10-1 to 10-4, respectively. Theterminating resistors 30, 30-1 to 30-4 are each connected to aterminating voltage (Vtt) with a lower impedance.

Herein, the coupling lengths of the directional couplers, that is, theparallel wiring lengths of the parts of the main line 20 and the subcouplers 20-1 to 20-4 are represented by L1 to L4, respectively.

FIG. 4 shows analysis results of the amplitudes of signals that aretransmitted to the DRAMs 10-1 to 10-4 with the structure shown in FIG.1, which is obtained through a circuit analysis simulation. In theconditions of analysis, the drive pulses is first outputted from the MC1 and consist of random pulses of 32 patterns. As a result, the drivepulses include the effects of the intersymbol interference (ISI). Theoperating frequency is 1.3 Gbps. In FIG. 4, the axis of abscissaexpresses the coupling lengths Li (herein, L1 to L4 are represented byLi) of the respective directional couplers, and the axis of ordinateexpresses generated peak voltages Vsw.

The definitions of the waveforms are shown in FIG. 5. FIG. 5A shows adrive waveform, and FIG. 5B shows a crosstalk signal (coupler signal)waveform which is a waveform at a DRAM input section. In FIG. 5B, thesignal amplitude at the DRAM input section is Vsw, the voltage variationat a peak section is Vv, a threshold potential is Vth, and jitters atVth is Tj. The solid line in FIG. 4 indicates a generated signal peakvoltage with respect the length Li at the DRAM 10-1, and the dotted lineindicates a generated signal peak voltage with respect the length Li atthe DRAM 10-4.

It is found from FIG. 4 that the signal amplitude at the position of theDRAM nearer to the MC1 is larger when the coupling length Li is thesame. It is found that, for example, in order that the signal amplitudeVsw at the DRAM 10-1 generates 200 mV, L1=17 mm is acceptable, whereasin the DRAM 10-4, L4=25 mm is required.

For facilitation of design, in the case where the coupling length Li isset up with pitches of 5 mm, under the simulation, the following lengthscan ensure 200 mV which is substantially equal in the signal amount withrespect to the respective DRAMs 10-1 to 10-4 under the conditions ofExpression (4).L1=15 mm, L2=20 mm, L3=20 mm, L4=25 mm

In the conventional art, since all of the coupling lengths are set to 25mm, the signal amplitude at the DRAM 10-1 is 260 mV, and the signalamplitude at the DRAM 10-4 is 200 mV which is different by 60 mV. Forthat reason, the delay times of the receivers within two DRAMs aredifferent from each other, and a timing margin is reduced. In an exampleof design, since a delay difference of the receiver is about 110 ps withrespect to an input amplitude voltage difference of 100 mV, 60 mV meansthe delay variation of 66 ps. Also, since the amount of jitters Tj ofthe directional coupler in this case is 137 ps, when the amount ofjitters and the delay variation of the receiver are added up, thevariation of 203 ps is obtained.

On the contrary, according to this embodiment, the random pulse isdriven by 1.3 Gbps, all of voltages at the DRAMs 10-1 to 10-4 becomesubstantially equal to each other, and the maximum of the amount ofjitters at the directional couplers is 115 ps from the simulationresult, which is smaller than that of the conventional art by 88 ps eventaking the receiver variation into consideration. This corresponds to10% of the operating cycle, and the timing margin can be ensured asmuch, or higher speed can be performed as much.

As described above, since the lengths of the directional couplers areadjusted according to the signal amount as indicated by Expression (4),a variation in the signal amount can be suppressed, and the jitters canalso be suppressed. For that reason, a difference in the delay amount ofthe receivers within the respective DRAMs 10-1 to 10-4 can be minimized,and the timing margin of the bus can be increased. That is, it is foundthat this structure is effective for the high speed of the bus. Inaddition, since the respective intervals of the DRAMs 10-1 to 10-3 arenot required to be adjusted to the longest directional coupler length ofthe DRAM 10-4, an interval between the DRAMs 10-1 and 10-2 and aninterval between the DRAMs 10-2 and 10-3 can be narrowed. This enablesthe high density.

As a second embodiment, a description will be given of a structure inwhich the generated signal amount is held constant by changing theintervals between the wirings while holding the coupling lengths of thedirectional couplers constant with reference to FIGS. 6 and 7.

Since the structural elements of FIG. 6 are identical with those of FIG.1, only differences will be described. The sub coupling wirings 20-1 to20-4 have the same length. However, intervals between the parts of themain line 20 and the parallel wirings of the sub couplers 20-1 to 20-4which constitute the directional couplers are different from each other.It is assumed that the wiring interval between the sub coupling wire20-1 and the main line 20 is w1, and similarly the wiring intervalsbetween the sub coupling wirings 20-2 to 20-4 and the main line 20 arew2, w3 and w4, respectively. When the wiring-interval is indicatedrepresentatively, the wiring interval is represented by wi with themeaning of i-th.

FIG. 7 is a bird's eye view showing the directional couplers disposedwithin a printed board 10. In the figure, cuboids are made of metalconductor. The main line 20 that constitutes the directional coupler andthe sub coupling wiring 20-1 in front of the main line 20 are wired atan interval of w1, and the main line 20 and the sub coupling wiring 20-2are wired at an interval of w2 that is narrower than w1. Since thewirings are surrounded by power layers at both of upper and lowerportions, FIG. 7 is a diagram constituted by strip lines. The microstrip line having an air layer at one end and a power layer only at theother end establishes the following discussions.

The directional couplers different in the wiring interval w1 aredifferent in the degree of coupling from each other. That is, thedirectional coupler wider in the interval wi is lower in the degree ofcoupling. This is because both of the capacitive coupling and theinductive coupling between two lines are reduced. In FIG. 7, thedirectional couplings are constituted in a horizontal direction, but maybe constituted in a vertical direction.

The coupling coefficient Kb of the directional coupler is defined asrepresented by Expression (5).Kb=(generated signal amount at a near end of the directionalcoupler)/(drive pulse voltage of the main coupling line)   (5)

As described above, this is called “backward crosstalk coefficient”, andtakes a constant value when the rise time of the drive pulse is shorterthan the propagation delay time of reciprocating of the directionalcouplers. In this case, when it is assumed that the capacitance matrixof two lines is [C], and the inductance matrix of two lines is [L] inthe wiring structure of FIG. 7, the relationship of the followingexpressions are satisfied. In the expressions, the elements of therespective matrixes are represented by subscripts.Zod=Sqrt[(L 11+L 12)/(C 11+C 12)]  (6)Zev=Sqrt[(L 11−L 12)/(C 11−C 12)]  (7)Kb=½((Zev−Zod)/(Zev+Zod)}  (8)Where Sqrt is a square root. The backward crosstalk coefficient Kb isrepresented by the elements of [C] and [L].

In FIG. 6, zones 1, 2, 3 and 4 are distinct in the order closer to theMC 1 in a zone where the main line 20 constitutes the directionalcouplers for convenience. The amount of attenuation of the drive pulsethat progresses a section i is represented by αi, and the degree ofcoupling of the directional coupler in the i-th zone is represented byKbi. When it is assumed that the drive pulse that is inputted to thezone 1 of the main line 20 is V0, the signal amount Vi that is generatedat the near end of the sub coupling line in the zone i is represented bynumeral (9).V 1=Kb 1*V 0V 2=Kb 2*V 0*α1V 3=Kb 3*V 0*α1*α2V 4=Kb 4*V 0*α1*α2*α3Vi=Kbi*V 0*Πi (αi)   (9)Where Πi (αi)=α1*α2*α3 . . . *αi. The attenuation is different dependingon the frequency component, and is larger with the higher frequencycomponent due to the skin effect or the conductance loss. That is, alarge amount of high frequency components exist in the transitionsection (rise section, fall section) of the NR signal that propagates onthe main line 20. This regulates the peak value of a signal that isgenerated on the near end of the sub coupling line of the directionalcoupler. Therefore, it is natural that the amount of attenuation on thetransition section is set to α. However, a ratio of the signal Vi toVi+1 which are induced by making the coupling coefficients Kb of therespective directional couplers identical with each other issubstantially equal to αi. As is understood from Expression (9), whenKbi is so adjusted to meet. “Kbi*Πi (αi)=constant”, the generated signalamounts at the near ends of the sub coupling lines are substantiallyequal to each other. In this embodiment, the coupling lengths of thedirectional couplers are constant, Expression (10) may be satisfied withαi≈α.Kbi=1/(α{circumflex over ( )}(i−1))   (10)where symbol “x{circumflex over ( )}i” expresses i power of x. In thedata transfer of about 1 Gps, attenuation cannot be ignored. However,since the attenuation is not so large, Expression (10) can be modifiedinto Expression (11) with α=(1−x) $\begin{matrix}\begin{matrix}{{Kbi} = {1/\left( {\left( {1 - x} \right)\quad\hat{}\quad\left( {i - 1} \right)} \right)}} \\{= {{Kb1}*\left( {1 + {\left( {i - 1} \right)*x}} \right)\quad\left( {i > 1} \right)}}\end{matrix} & (11)\end{matrix}$

As with FIG. 1, as a result of analyzing the circuit through simulation,in the case where Kb of the directional couplers is equal to each other,and the coupling length is 25 mm, the attenuation coefficient α issubstantially 0.9, and x is 0.1.

Then, simulation is conducted in a system where the wiring interval wiis changed so that Kb2 is 1.1 times Kb1, Kb3 is 1.2 times Kb1, and Kb4is 1.3 times Kb1. The value of wi in this case is represented byExpression (12).w 1=0.160 mm, w 2=0.135 mm, w 3=0.15 mm, w 4=0.1 mm   (12)

As a result of the simulation, it is found that the variation of Vswbetween DIMM in this embodiment is 28 mV with respect to 61 mV, that is,about half of 61 mV when wi is constant. Jitters of the bus wiring aresubstantially the same, that is, 100 ps.

For that reason, although the effect of reducing the wiring jitters ofthe bus is little, since a variation in the input amplitude to thereceiver between DIMM is low and a variation in the delay time of thereceiver is low, this structure is effective for high speed.

A third embodiment will be described with reference to FIG. 8. In thisembodiment, even in the case of using the directional coupler having acoupling length different from that in the first embodiment, the moduleintervals are held constant.

The DRAMs 10-1 to 10-4 are mounted on daughter boards indicated by 60-1to 60-4, respectively, and connected to a mother board 100 throughconnectors 50-1 to 50-4. An MC 1 is mounted on the motherboard 100, andthe main line 20 and sub coupling lines 20-1 to 20-4 that constitute thedirectional couplers in association with parts of the main line 20 areformed on the motherboard 100. A large number of DRAMs are mounted onthe daughter boards 60-1 to 60-4, but only one DRAM is shown in FIG. 8for simplification.

A drive pulse from the MC 1 propagates on the main line 20 of thedirectional couplers, and signals that are generated by the directionalcouplers are transmitted to the DRAMs 10-1 to 10-4 through connectors50-1 to 50-4, respectively. The same is applied to the reversepropagation of the data signal.

In this embodiment, the coupling lengths of the directional couplers arelonger as the directional couplers are farther away from the MC 1 as inthe first embodiment. However, the intervals of the modules 60-1 to 60-4are constant in this embodiment. In the case where a power consumptionof semiconductors such as the DRAMs 10-1 to 10-4 that are mounted on themodules 60-1 to 60-4 is large, intervals of some degree are required forheat radiation depending on the device. From the viewpoint of heatradiation, the structure in which the module intervals are constant hassuch an advantage that the installation structure is simplified even inthe case where thermal diffusion is made by air since heat sources getuniform. For that reason, even in the case where the coupling lengths ofthe directional couplers are different from each other, the heatradiation property of the device is more excellent when the intervals ofthe modules are made constant. In this embodiment, the MC 1 and theDRAMs 10-1 to 10-4 which are connected through the bus can be madeidentical in the signal amplitude with each other, and the concentrationof heat can be prevented with respect to the high power consumptionDRAMs.

A fourth embodiment will be described with reference to FIG. 9.

In a semiconductor such as DRAM which transfers data, its bus frequentlyhas a control signal and an address signal (C/A signal) in addition to adata signal. This embodiment is an example in which the directionalcouplers are constituted within a memory module in the case where theC/A signal is transferred by using the directional couplers.

It is difficult to adjust the intervals of the DRAMs because a largenumber of DRAM chips are mounted on a limited space in the DRAM memorymodule. For that reason, in the case where the C/A signal of thehigh-density DRAM module is transferred by the directional couplers, itis desirable to hold the generated signal amount constant by changingthe coupling coefficients for each of the couplers as in the secondembodiment.

In FIG. 9, the DRAMs 10-1 to 10-4 are mounted in the memory module 60,and wirings of the DRAMs 10-1 to 10-4 and the MC 1 are shown. Reference20 a denotes a wiring that is used within the mother board 100 andextends from the MC1 to a connector 50. The wiring 20 a is connected toa wiring 20 b within the daughter board 60. The wiring 20 b is matchedand terminated, and parts of the wiring 20 b and the sub coupling lines21-1 to 21-4 constitute the directional couplers within the daughterboard 60. The directional couplers that are connected to the DRAMs 10-1to 10-4 have the coupling lengths as in the second embodiment, but thecoupling coefficients Kb are changed with different wiring intervals,respectively. The Kb is determined at the same rate as that in thesecond embodiment. That is, the coupling coefficients (Kb) of thedirectional couplers that are positioned farther away from the MC 1 aremade larger. For that reason, the amplitudes of the input signals thatare generated by the directional couplers and propagated to the DRAMs10-1 to 10-4 are substantially identical with each other. In addition, avariation in the signal amplitude and jitters can be minimized ascompared with a case in which the wiring intervals wi are not changed.That is, it is found that the equal signals are generated. For thatreason, there is an effect of reducing the jitters as in theabove-mentioned embodiments. In this embodiment, the directionalcouplers are used for the C/A signal. The same effects can be obtainedeven if the directional couplers are used for data.

A fifth embodiment will be described with reference to FIG. 10. Thisembodiment is an example where, in a memory bus that transfers data byusing the memory module 60 shown in the fourth embodiment, directionalcouplers for a C/A signal are incorporated into the module, anddirectional couplers for a data signal are incorporated into themotherboard 100.

The memory modules 60-1 to 60-4 have module substrates of the samestructure on which a large number of DRAMs are mounted. The respectiveDRAMs are represented by numerals 10-1 to 10-4. The modules are roughlyclassified into pins and pads for the C/A signal and for the datasignal, and those signals are connected to one another throughconnectors not shown.

The C/A signals are indicated by reference numeral 23 and wired to therespective modules 60-1 to 60-4 from the MC 1. The data signals areindicated by reference numeral 22 and wired to the respective modules60-1 to 60-4 from the MC 1. The number of data signals is identical withthe number of data signal pins of the modules, and the modules used in aPC/server have 32, 62 and 144 signal lines. The wiring structures forthe data signal which include those plural wirings are substantiallyequal to each other.

FIG. 10 is a top view in the case where the memory modules 60-1 to 60-4are vertically mounted on the motherboard 100, which is sketched for thepurpose of clarifying the structure of wirings. The data signal wirings22 from the MC 1 to the respective DRAMs 10-1 to 10-4 are transmittedand received through the directional couplers, and the directionalcouplers are constituted on the motherboard. The coupling lengths areindicated by L1, L2, L3 and L4 in the order closer to the MC 1. Thisstructure is identical with that in the first embodiment. For thatreason, the coupling lengths of the directional couplers which arefarther away from the MC 1 are longer.

For that reason, the generated signal amount of the data signal issubstantially identical with respect to each of the DRAMs, which has theeffects of reducing the variation in the signal voltage and jitters andperforming high speed.

Since the MC 1 and the modules 60-1 to 60-4 are connected to the C/Asignals at 1:1, all of the DRAMs have substantially the same signalamount as in the fourth embodiment, which has the effects of reducingthe variation in the signal voltage and jitters and performing highspeed. That is, there is the effect of reducing jitters with respect todata as well as the C/A signal.

A sixth embodiment will be described with reference to FIG. 11.

In this embodiment, the directional couplers that generate the equalsignal amount are applied to wirings in which the main line is formed bya folded wiring so as to provide high density.

Reference numeral 20 denotes a folded wire drawn out of the MC 1. Alarge number of DRAMs are mounted on the memory modules 60-1 to 60-4,and are connected to the bus through the connectors 50-1 to 50-4,respectively. The sub coupling lines 20-1 to 20-4 are drawn from themodules 60-1 to 60-4 respectively that are arranged in the order closerfrom the MC 1. The sub coupling lines 20-1 to 20-4 are arranged in thestated order of the sub coupling lines 20-1, 20-4, 20-3 and 20-2 withthe lengths of L1, L4, L2 and L3, respectively. The DRAM 10-1 isconnected with the wiring 20-1 with the length L1, the DRAM 10-2 isconnected with the wiring 20-2 with the length L4, the DRAM 10-3 isconnected with the wiring 20-3 with the length L2, and the DRAM 10-4 isconnected with the wiring 20-4 with the length L3. This example ischaracterized in that the directional couplers are arranged not at thedistances from the MC 1 but at the distances from the main line 20.

As described above, since the main line 20 is folded, and the subcoupling lines are constituted with respect to the main line 20, thehigh density of the module can be performed, and the signal amplitudesthat are generated from the directional couplers can be made constant.Also, when the sub coupling lines 20-2 and 20-3 are so arranged as notto overlap with each other, an interval L23 between the modules 60-2 and60-3 can be reduced. This is because there is no directional coupler inthat zone.

As a result, the directional couplers that have the memory modules ofthe same number with high density and generate the equal signal amountcan be constituted.

A seventh embodiment will be described with reference to FIG. 12.

This embodiment is an example in which the directional couplers are soconstituted as to generate the equal signal amount in a bus system wherethe main line is folded within the module.

The main line 20 from the MC 1 is connected and wired to the interior ofthe module 60-1 through a signal layer disposed within the motherboard100 and a connector 50-1. The wiring 20 within the module 60-1 and thesub coupling lines 20-1 and 20-2 constitute the directional couplerswhich are connected to the DRAMs 10-1 and 10-2. The main line 20 isfolded within the module 60-1, and is again wired to a connector 50-2 inthe signal layer within the motherboard 100 through the connector 50-1.In the same manner, the main line 20 within the modules 60-2, 60-3 and60-4 is terminated by terminating resistors on the motherboard. In thisexample, the modules 60-1 and 60-2 are identical in the structure witheach other, and when it is assumed that the coupling lengths of thosetwo directional couplers are L1 and L2, respectively, a relationship ofL1≦L2 is satisfied. In addition, the modules 60-3 and 60-4 are identicalin the structure with each other, and when it is assumed that thecoupling lengths of those two directional couplers are L3 and L4,respectively, a relationship of L3≦L4 is satisfied. A relationshipbetween those two kinds of modules is represented by Expression (13).(L 1≦L 2)≦(L 3≦L 4)   (13)

With the above structure, the wiring lengths of the directional couplershave the same effects as those in the first embodiment, and thegenerated crosstalk signal amounts are made identical with each other,thereby making it possible to suppress jitters. For that reason,differences in the delay amount of the receivers within the respectiveDRAMs 10-1 to 10-8 can be supported, and the timing margin of the buscan be increased. That is, this shows that this structure is effectivefor high speed of the bus.

In the directional coupling memory system that conducts a bus connectionby inserting the module into the connector, even in the case where thelengths of the directional couplers become longer as the directionalcouplers are positioned farther away from the MC 1, the kind of modulesis limited to two kinds, thereby forming both of a reduction in thecosts and an improvement in the performance.

An eighth embodiment will be described with reference to FIG. 13.

This embodiment is to aim for higher speed than that in the aboveembodiments.

The structure is substantially identical with that in the firstembodiment, but different in the structure of the directional couplerstherefrom.

In this embodiment, the wiring intervals wi between two lines (the mainline and each of the sub coupling lines 20-1 to 20-4) which constitutethe directional couplers are different from one another, and thecoupling lengths Li therebetween are different from one another.w1≧w2≧w3≧w4   (14)L1≧L2≧L3≧L4   (15)

In Expression (14), the wiring intervals wi of the directional couplersof the nearer end when being viewed from the MC 1 are longer, and forthat reason, the backward crosstalk coefficients Kb of the directionalcouplers of the farther end are higher. However, the differences of Kbcancel the dull effect as the drive pulse signal propagates on the mainline 20. Also, the coupling lengths Li are shorter with the farther endsin this embodiment although the coupling lengths Li are longer with thefarther ends in the first embodiment. This means that since the drivepulses are dulled more with the farther ends, the tail sectionsgenerated become longer with the farther ends. For that reason, in orderto suppress an increase in the tail sections and an increase in jitterswhich are attributable to the dull waveform of the drive pulse, thecoupling lengths Li are shortened. Since the structure completelyopposite from that in the first embodiment is made, the signal amount isreduced with the decrease in the coupling lengths Li, but this iscompensated by increasing the coupling coefficient Kb. That is, sincethe coupling lengths Li and the wiring intervals wi are constituted asexpressed in Expressions (14) and (15), the generated crosstalk signalshave the comparable signal amplitude and the comparable signal timewidth. For that reason, it is possible to suppress an increase injitters and the delay time jitters of the receivers, which areattributable to the wiring. For that reason, this structure is suitablefor data propagation of further ultrahigh speed as compared with that inthe first embodiment.

The eighth embodiment will be described with reference to FIG. 14.

FIG. 14 shows a drive 4 of a semiconductor device which is mounted onthe MC 1 or the DRAMs 10-1 to 10-4 in the above embodiments, and thisembodiment aims at the suppression of jitters by eliminating the tailsection.

Before the structure of this embodiment will be described, the principleof a reduction in jitters will be described using waveforms withreference to FIG. 15.

As shown in FIG. 3, in the case of conducting the high speed datatransfer, the intersymbol interference on the bus wiring occurs mainlybecause the tail section of the crosstalk signal is superimposed on datasubsequent to that crosstalk signal. For that reason, when the tailsection of the crosstalk signal is reduced, the mount of jitters whichis the intersymbol interference of the bus can be reduced.

FIG. 15A shows a drive pulse for reducing the tail section, and FIG. 15Bshows a crosstalk signal waveform therefore. A dotted line 70 is aconventional waveform which is identical with the drive pulse of FIG.3B, and is superimposed on a solid line till a time tod. A solid line 80represents the drive pulse in this embodiment.

A pulse is driven with an amplitude V1 at a time “0”, and after a timetod, a pulse having a reverse polarity to data is driven with (−α*V1).In this example, α is a coefficient which is about 10 to 20%. FIG. 15 isan explanatory diagram of the waveform which is driven from L to H, andsimilarly in the case of the waveform driven from H to L, (+a*V1) havinga reverse polarity to data is driven after Tod.

A crosstalk waveform to the drive pulse 70 indicated by the dotted lineis represented by a waveform 75 indicated by the dotted line in FIG. 15Bwhereas a crosstalk waveform to the drive pulse 80 indicated by thesolid line in FIG. 15A is represented by a waveform 85 indicated by thesolid line in FIG. 15B. The waveforms 75 and 85 are superimposed on eachother till the time tod. This is because the drive pulses 70 and 80 thatpropagate the directional couplers are identical with each other tillthe time tod. However, after the time tod, since the drive pulseindicated by the solid line is driven with the reverse polarity and alsowith the amplitude (−α*V1), a signal of the reverse polarity isgenerated by the directional coupler in response to the above drivepulse, and superimposed on the waveform 75 indicated by the dotted line.For that reason, the superimposed waveform becomes the maximum (−α*V1)after a time (tod+tr), and is superimposed on the waveform 75 indicatedby the dotted line whereby the tail section is reduced in size asrepresented by the waveform 85 of the solid line. In this example, Vphas a relationship of Vp=Kb*V1 as with Expression (9) when it is themaximum of the crosstalk generated by the directional coupler andsatisfies Expression (1). Reference tr is a rise time of the drivepulse, and at that time, the crosstalk waveform becomes the maximum.

As described above, since the drive waveform is generated as with thewaveform 80 indicated by the solid line in FIG. 15, the tail section ofthe crosstalk can be minimized with the result that the intersymbolinterference of the bus is reduced, which contributes to a reduction injitters and high speed.

A driver that realizes the waveform is shown in FIG. 14. FIG. 14 mainlyshows the circuit structure at a final stage of the driver 4. In thisembodiment, the driver is made up of a push-pull driver of C-MOS.However, it is needless to say that the waveform shown in FIG. 15 can begotten even when an open-drain type interface is used.

In FIG. 14, the driver of the final stage is made up of transistors Mlto M 4, and its data output to an output pad 5 is controlled accordingto a data signal (DATA) and an output enable (OE) signal. OE is negated,and the transistors M1 to M4 generate outputs according to DATA. M3 andM4 of those transistors are driven for only a given period of time.Those transistors M3 and M4 are controlled by delay circuits 90, 91 andexclusive ORs X1, X2. In other words, the transistors M2 and M4, or M1and M3 are driven at the same time according to the DATA signal. Sincethe inputs of X1 and X2 becomes equal to each other by means of thedelay circuits 90 and 91, the transistors M3 and M4 are negated. In thisexample, since the drain-to-source impedances of the transistors M3 andM4 correspond to a in FIG. 15B, the gate widths of the transistors canbe so adjusted as to control α.

The delay circuits 90 and 91 have delay times adjusted by delay holdingcircuits (registers) 92 and 93, respectively. The delay circuits 90 and91 are constituted in such a manner that a plurality of minute delayelements are connected in series, and those outputs change over by meansof a switch, thereby making it possible to delay the signals. Since thedelay circuits 90 and 91 can select the number of minute delay elementsto be connected according to the values of the registers 92 and 93,respectively, by means of the switch, the delay amount can be discretelyand continuously adjusted. The registers 92 and 93 hold values thatallow the delay times that are substantially equal to tod of FIG. 15 tooccur.

Since M1 and M3, or M2 and M4 are driven for period of timescorresponding to the delay circuits 90 or 91, respectively, the driveimpedances are decreased for that period of time, and it is understoodthat the waveform 80 in FIG. 15A is obtained.

The driver 4 is used for a signal output circuit of the MC 1 in FIG. 1,and the MC 1 is driven as indicated by the waveform 80 in FIG. 15B withrespect to each of the DRAMs 10-1 to 10-4 at the time of write. As aresult, in each of the directional couplers 20-1 to 20-4, since the tailsection is reduced, the intersymbol interference is reduced, and thetiming margin is increased. That is, the high speed operation can beperformed.

Likewise, the driver 4 is used with respect to the DRAMs 10-1 to 10-4,and the waveform 80 in FIG. 15A is outputted at the time of read. As aresult, in each of the directional couplers 20-1 to 20-4, since the tailsection is reduced, the intersymbol interference is reduced, and thetiming margin is increased. That is, the high-speed operation can beperformed.

Now, setting of tod will be described with reference to FIG. 16.

As in FIG. 10, data is transferred between the MC 1 that is mounted onthe motherboard 100 and the memories 10 that are mounted on the memorymodules 60-1 to 60-4. The C/A signal is transferred through the wirings23, and the data signal is transferred through the wirings 22. In thisexample, the data is transmitted and received by the directionalcouplers disposed in the motherboard 100, and the C/A signal istransmitted by the directional couplers disposed in the memory modules60-1 to 60-4. In the data signal, the directional couplers have thecoupling lengths L1, L2, L3 and L4 disposed within the motherboard 100with respect to the modules 60-1 to 60-4. The coupling lengths L1 to L4are determined as represented by Expression (4) as in the firstembodiment. For that reason, there is no difference in the generatedsignal amount due to distances from the MC 1. The drivers shown in FIG.14 are incorporated into the MC 1 and the memories 10, and can drive thewaveform indicated by the solid line 80 in FIG. 15 at the time of drive.The setting of tod will be described in the MC 1 and the memories 10,separately.

In the case of the MC 1, the MC 1 is connected with wirings 24-1 to24-4, and those wirings 24-1 to 24-4 have wiring lengths having the samepropagation delay times as the reciprocating times of the directionalcouplers L1 to L4. For that reason, the MC 1 can recognize thereciprocating delay time of the coupling length L1 of the directionalcoupler with respect to the module 60-1 by measuring the delay time ofthe wiring 24-1. Similarly, the coupling lengths L2 to L4 of thedirectional couplers can be recognized by measuring the propagationdelay times of the wirings 24-2 to 24-4. On the basis of thatinformation, values of the registers 93 and 94 within the driver 4 inFIG. 14 which are mounted in the MC 1 can be set. In the case where theMC 1 transmits write data using the above information, a pulse having areverse polarity to data can be driven for the time tod corresponding tothe reciprocating delay times of the coupling lengths L1 to L4 of thedirectional couplers that are connected to the modules 60-1 to 60-4;therefore, the intersymbol interference is reduced, and high speed canbe performed.

In the case of the memory 10, delay time information that is stored inrewritable ROMs (EPROMs) 15-1 to 15-4 that are mounted in the memorymodules 60-1 to 60-4, respectively, is transferred to the registers 93and 94 within the driver 4 of the memory 10 prior to data transmission.More specifically, the MC 1 writes the reciprocating propagation timeinformation on the coupling lengths L1 to L4 of the directional couplerscorresponding to the respective modules 60-1 to 60-4 into EPROMs 15-1 to15-4 respectively in advance. The write timing may be set immediatelyafter the power is turned on or every given time. The EPROMs 15-1 to15-4 hold the written information, and the values are transmitted to thememories 10 through wirings 25. The delay time information may betransmitted to the memories 10 by writing the information into therespective memories using boundary scan information by the MC 1, or bygiving the information to the respective memories 10 according to arequest of the memories 10 by the EPROMs 15-1 to 15-4.

The MC 1 writes the reciprocating propagation delay time information ofthe directional couplers into the EPROMs 15-1 to 15-4, and stores thatinformation in the registers 93 and 94 within the memories 10. With thisstructure, the memories 10 can each send tail section reduction drivepulses corresponding to the coupling lengths of the directional couplerswith respect to read data of memory access. As a result, the intersymbolinterference is reduced, and jitters are also reduced.

In the above example, the DRAMs are controlled through the boundary scancircuit. However, the boundary scan circuit may be changed over by ametal mask during manufacture of the DRAMs.

In addition, the MC 1 may use respective different values α for theDRAMs 10-1 to 10-4. For example, α=10% may be used for the DRAMs 10-1and 10-2, and α=20% may be used for the DRAMs 10-3 and 10-4. Thedifferent values a can be achieved by adjusting the output impedances ofthe driver 4, and can be realized by connecting it to the transistors M3and M4 in FIG. 14 in parallel and switching over those transistors.Since tod and α are constituted for each of the DRAMs in this manner,the tail section can be reduced while the signal amplitude is heldconstant in any DRAM, thereby making it possible to suppress theintersymbol interference. The same effects are obtained in FIG. 6 aswell as FIGS. 8 to 13.

In this embodiment, the waveform 80 in FIG. 15A is generated by thedriver. However, the same effects can be obtained if the same waveformcan be generated even by other methods. For example, the waveform havingtod and a as shown in FIG. 15 can be generated by a wiring having animpedance that is different form the characteristic impedance of themain line 20.

In the first advantages of the present invention, the wiring lengths ofthe directional couplers that are formed of two wirings on the printedboard is made longer as the directional couplers are located fartheraway from the MC, thereby making the crosstalk signals that aregenerated by the directional couplers identical in any directionalcouplers. This makes it possible to compensate for the drive pulse beingmore dulled due to the skin effect and dielectric loss as the drivepulse propagates to the farther end.

Jitters generated by the directional couplers are made constantregardless of the position of the directional couplers, thereby makingthe timing margin of the entire system constant.

In the data transfer between the bus master 1 and the bus slaves 10-1 to10-4, a difference in the amplitude of the signal waveforms, which isgenerated according to the arrangement, can be eliminated. As a result,a variation in the delay of the receivers is greatly suppressed, therebybeing capable of making the noise sensitivities of the receiversconstant. Consequently, higher speed operation can be performed. Thatis, the present invention is effective for the high speed of the bus.

In the second advantages of the present invention, even in the casewhere the coupling lengths of the directional couplers areinsufficiently obtained, or the bus slaves must be arranged at regularintervals due to the structure of the system as with the memory module,the bus slaves are arranged at regular intervals so that the couplinglengths of the directional couplers become the longest, and theintervals of the wirings is more narrowed as the wirings are farther,thereby being capable of making the crosstalk signal amount generated ineach of the bus slaves constant. With this structure, both of the equalinterval arrangement and the equal signal generation can be performed.

In the third advantages of the present invention, since waveformsgenerated by the directional couplers include the tail sections, theintersymbol interference due to the tail sections causes jitters.However, since a pulse having a reverse polarity to data is driven bythe driver a times the drive pulse amplitude (about 10 to 20%) for thereciprocating delay time of the directional couplers, the tail sectioncan be eliminated. For that reason, it is possible to make the signalamplitude constant and to eliminate the intersymbol interference causedby the tail section. Hence, higher-speed operation can be performed.

INDUSTRIAL APLICABILITY

According to the present invention, in the memory system to which aplurality of DRAM memory modules are connected, since data can betransferred between the memory controller and the respective modules athigh-speed by suppressing jitters, the present invention is applicableto a memory system that can perform data transfer at high speed as theentire system.

1. A bus system that transfers data between a plurality of semiconductordevices, wherein: a first wiring is drawn out of a first semiconductor,a plurality of wirings are arranged in parallel with the first wiring toconstitute directional couplers, and the wirings are each connected to asecond semiconductor device; and each of the directional couplers has adifferent coupling length so that signal amplitudes generated by theplurality of directional couplers may be substantially the same.
 2. Thebus system according to claim 1, wherein when it is assumed that lengthsof n directional couplers connected are L1, L2, L3, . . . Ln in theorder nearer to the first semiconductor, generated signal amounts of thedirectional couplers are substantially the same by satisfying L1≦L2≦L3≦. . . ≦Ln.
 3. The bus system according to claim 2, wherein when it isassumed that the second semiconductor comprises four secondsemiconductors, and lengths of the directional couplers are L1, L2, L3and L4 in the order nearer to the first semiconductor, a differenceamong the coupling lengths of L1, L2, L3 and L4 is within 10 mm.
 4. Thebus system according to claim 1, wherein when it is assumed thatintervals between two parallel lines that constitute n directionalcouplers connected are w1, w2, w3, . . . wn in the order nearer to thefirst semiconductor, the degrees of coupling of the directional couplersare changed by satisfying w1≧w2≧w3≧ . . . ≧wn, and generated signalamounts of the directional couplers are substantially the same.
 5. Thebus system according to claim 4, wherein when it is assumed that thedegree of coupling of an i-th directional coupler from the firstsemiconductor is Kbi, the i-th directional coupler has the degree ofcoupling Kbi given by Kbi=Kbi*(1+(i−1)*x), where the degree of couplingKb1 of the first directional coupler has a coefficient of x=0.1 to 0.2.6. A printed circuit board in the bus system of claim 2 or 3, whereinthe directional couplers have the coupling lengths that satisfyL1≦L2≦L3≦ . . . ≦Ln.
 7. A printed circuit board in the bus system ofclaim 4 or 5, wherein the directional couplers are provided which havethe wiring intervals that satisfy w1≧w2≧w3≧ . . . ≧wn.
 8. The bus systemaccording to claim 2, 3, 4 or 5, wherein: the first semiconductor andthe directional couplers are mounted on a motherboard; a plurality ofthe second semiconductors are mounted on a plurality of daughter boards;the plurality of daughter boards are connected to the motherboardthrough connectors; and intervals of the plurality of daughter boardsare constant independently from the lengths of the directional couplers.9. A memory module for use in the bus system of claim 4 or 5, wherein: aplurality of memories are mounted instead of the plurality of secondsemiconductors, directional couplers used for signal transmissionbetween the first semiconductor and the memories are disposed within thememory module, and the memories are arranged at regular intervals withinthe memory module; and when it is assumed that intervals between twoparallel lines that constitute n directional couplers connected to thebus system are w1, w2, w3, . . . wn in the order nearer to the firstsemiconductor, the degrees of coupling of the directional couplers arechanged by satisfying w1≧w2≧w3≧ . . . ≧wn, and generated signal amountsof the directional couplers are substantially the same.
 10. A bus systemusing the memory module of claim 9, wherein: a data signal istransferred through a data signal bus by using directional couplersdisposed within a motherboard, and a control signal is transferredthrough a control signal bus by using directional couplers disposedwithin a daughter board; when it is assumed that lengths of directionalcouplers in each of n memory modules formed on the motherboard are L1,L2, L3, . . . Ln in the order nearer to the memory controller, L1≦L2≦L3≦. . . Ln is satisfied; when it is assumed that intervals between twoparallel lines that constitute n directional couplers connected to thecontrol signal bus within the memory module are w1, w2, w3, . . . wn inthe order nearer to the first semiconductor, the degrees of coupling ofthe directional couplers are changed by satisfying w1≧w2≧w3 . . . ≧wn,and generated signal amounts of the directional couplers aresubstantially the same in all of the memories.
 11. The bus systemaccording to claim 8, wherein: the first semiconductor and thedirectional couplers are mounted on a motherboard; the plurality ofsecond semiconductors are mounted on a plurality of daughter boards; theplurality of daughter boards are connected to the directional couplersof the motherboard through connectors; a wiring extending from thesecond semiconductors is folded within the mother board; when it isassumed that lengths of n directional couplers connected to the bussystem are L1, L2, L3, . . . Ln in the order nearer to the firstsemiconductor along the wiring, generated signal amounts of thedirectional couplers are substantially the same by satisfying L1≦L2≦L3≦. . . ≦Ln.
 12. The bus system according to claim 8, wherein: one busmaster is mounted on a motherboard, a plurality of daughter boards arebus-connected to the motherboard through directional couplers andconnectors which are disposed within the daughter boards; the wiringextending from the second semiconductor is folded within the daughterboards; when it is assumed that lengths of two directional couplersformed in association with parts of the folded main line are L1 and L2in the order near to the first semiconductor along the wire, a firstmemory module satisfies L1≦L2; when it is assumed that lengths of twodirectional couplers formed by the folded wiring and the sub couplingwirings are L3 and L4 in the order nearer to the first semiconductoralong the wiring, a second memory module satisfies L2≦L3≦L4; and twofirst memory modules and two second memory modules are mounted on themother board in the order nearer to the first semiconductor.
 13. The bussystem according to claim 2 or 4, wherein: when it is assumed thatlengths of n directional couplers connected to the bus system are L1,L2, L3, . . . Ln in the order nearer to the first semiconductor,L1≦L2≦L3≦ . . . ≦Ln is satisfied; and when it is assumed that intervalsbetween two parallel lines that constitute n directional couplersconnected to the bus system are w1, w2, w3, . . . wn in the order nearerto the first semiconductor, the degrees of coupling of the directionalcouplers are changed by satisfying w1≧w2≧w3≧ . . . ≧wn, and generatedsignal amounts of the directional couplers are substantially the same.14. A bus system that transfers data between a plurality ofsemiconductor devices, wherein: a first wiring is drawn out of a firstsemiconductor, a plurality of wirings are arranged in parallel with thefirst wiring to constitute directional couplers, and the wirings areeach connected to a second semiconductor device; each of the directionalcouplers has a different coupling length so that signal amplitudesgenerated by the plurality of directional couplers may be substantiallythe same; and a drive pulse corresponding to a transmitted data signalis inputted to the directional couplers, a signal having a reversepolarity to the data signal is again inputted to the directionalcouplers with an amplitude that is 10 to 20% of the amplitude of thedrive pulse after a reciprocating delay time of the directionalcouplers, and the signal having the reverse polarity continues untilsubsequent data is received.
 15. A semiconductor device in the bussystem of claim 14, wherein: a high signal or a low signal is outputtedto a driver mounted on the first semiconductor or the secondsemiconductor according to output data; the semiconductor deviceincludes a delay time holding circuit for holding a reciprocating delaytime of the directional couplers used in the bus system; and thesemiconductor device includes a driver that outputs a signal reversingthe output data by 10 to 20% of the signal amplitude with the delay timeof the holding circuit immediately after the output data is transmitted,and continuously outputs the signal of the reverse polarity untilreceiving subsequent data.
 16. A main controller in the bus system usingthe semiconductor of claim 15, comprising: a plurality of delay timeholding circuit which holds a reciprocating wiring length time of thedirectional couplers connected to the respective memories according tothe respective directional couplers; and a driver which outputs a signalreversing the output data by 10 to 20% of the signal amplitude with thedelay time of the holding circuit to the memories immediately after theoutput data is transmitted to the memories, and continuously outputs thesignal of the reverse polarity until receiving subsequent data.
 17. Amemory in the bus system of claim 15, comprising: a plurality of delaytime holding circuit which holds a reciprocating wiring length time ofthe directional couplers connected; and a driver which outputs a signalreversing the output data by 10 to 20% of the signal amplitude with thedelay time of the holding circuit immediately after the output data istransmitted, and continuously outputs the signal of the reverse polarityuntil receiving subsequent data.
 18. A memory module in the bus systemof claim 15, wherein memories each having a delay time holding circuitare mounted, each of the memories reads a value of the delay timeholding circuit from an EPROM disposed within the memory module prior todata transfer, and all of the memories within the memory module have avalue corresponding to the same delay time in the delay time holdingcircuit.